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SX1211
WIRELESS & SENSING
0
1
Automatically starts when a sync word is detected (d)
Manually controlled by Fifo_fill
FIFO filling status/control (Buffered mode only):
If Fifo_fill_method = ‘0’: (d)
Fifo_fill
6
14
r/w/
c
Goes high when FIFO is being filled (sync word has been detected)
Writing ‘1’ clears the bit and waits for a new sync word (if Fifo_overrun_clr=0)
If Fifo_fill_method = ‘1’:
0
1
Stop filling the FIFO
Start filling the FIFO
Tx_done
5
14
r
Tx_done IRQ source
Goes high when the last bit has left the shift register.
Tx start condition and IRQ_0 source:
If Data_mode(1:0) = 01 (Buffered mode):
0
1
Tx starts if FIFO is full, IRQ_0 mapped to /Fifoempty (d)
Tx starts if FIFO is not empty, IRQ_0 mapped to /Fifoempty
Tx_start_irq_0
4
14
r/w
If Data_mode(1:0) = 1x (Packet mode):
0
Start transmission when the number of bytes in FIFO is greater than or
equal to the threshold set by MCParam_Fifo_thresh parameter (Cf section
5.2.2.3), IRQ_0 mapped to Fifo_threshold (d)
1
Tx starts if FIFO is not empty, IRQ_0 mapped to /Fifoempty
(d): “0”, should be set to “1”.
Res
3
14
r/w
Note: “0” disables the RSSI IRQ source. It can be left enabled at any time, and
the user can choose to map this interrupt to IRQ0/IRQ1 or not.
RSSI_irq
2
14
r/w/
c
RSSI IRQ source:
Goes high when a signal above RSSI_irq_thresh is detected
Writing ‘1’ clears the bit
PLL status:
PLL_locked
1
14
r/w/
c
0
1
not locked
locked
Writing a ‘1’ clears the bit
PLL_lock detect flag mapped to pin 23:
PLL_lock_en
0
14
r/w
0
Lock detect disabled, pin 23 is High-Z
1
Lock detect enabled(d)
RSSI_irq_thresh
Rev 8 – February 2013
7-0
15
RSSI threshold for interrupt (coded as RSSI)
(d): “00000000”
Page 61 of 92
www.semtech.com
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